Vias are an indispensable component of multilayer PCBs; typically, drilling costs account for 30% to 40% of the total PCB manufacturing cost. Simply put, every hole is referred to as a via. Vias can be divided into two categories based on their function: one establishes an electrical connection between different layers, and the other serves to secure or position components. Based on the manufacturing process, vias are classified into three types: blind vias, buried vias, and through-holes. Blind vias connect the top and bottom layers of a printed circuit board; they have limited depth and are primarily used to connect surface-level and internal traces. Buried vias are located inside the board and do not extend to the surface. Through-holes pass completely through the board and can be used for internal interconnections or component mounting. Through-holes are less expensive and are therefore commonly used in manufacturing.
Considerations for Via Design
Vias consist primarily of drill holes and pads, which determine their dimensions. In high-speed, high-density PCB designs, designers typically aim to make via dimensions as small as possible to preserve more routing space and reduce parasitic capacitance. However, reducing the hole diameter also increases costs. Via dimensions are constrained by manufacturing processes such as drilling and electroplating; smaller hole diameters require longer drilling times and may result in off-center positioning. Furthermore, a hole depth exceeding six times the drill diameter can compromise the quality of the copper plating. With advancements in laser drilling technology, microvia production has become feasible, enabling smaller via dimensions.
The Effect of Via Holes on Circuit Performance
Vias cause signal reflections and create impedance discontinuities in transmission lines. The equivalent impedance of a via is typically about 12% lower than that of the transmission line. Vias also have parasitic capacitance and inductance. Parasitic capacitance causes signal rise times to lengthen, affecting circuit speed. Parasitic inductance is a more serious issue in high-speed digital circuit design, as it can weaken the filtering effect of the power supply system.
Strategies for Using Via Holes
In high-speed PCB design, vias can have adverse effects. To minimize parasitic effects, the following strategies can be considered during the design process:
- Select appropriate via sizes based on cost and signal quality; smaller vias can be used for signal lines, while larger vias can be used for power and ground lines.
- Choose thinner PCBs to reduce parasitic parameters.
- Avoid signal layer changes as much as possible and minimize unnecessary vias.
- Drill vias for the power and ground lines as close as possible, and keep the trace lengths as short as possible. You can even connect multiple vias in parallel.
- Place ground vias near signal vias at layer transitions to provide a near-field return path for the signals.
- Use micro vias in high-density PCBs.
These strategies can minimize the negative effects of vias and improve the performance of PCB designs.
