Custom IC Substrates and
High-Precision Packaging SubstratesManufacturing

We specialize in the R&D and manufacturing of high-precision IC packaging substrates, covering mainstream packaging types such as BGA, CSP, FC, and SiP, and support BT, ABF, and FR4-based substrate materials. We offer stable mass production with line/space widths of 20/20 μm and can evaluate prototypes down to 15/15 μm, providing one-stop delivery from prototype validation to mass production.

Mass Production 20/20 μm (Reliable Delivery)
Sample size: 15/15 μm (To be evaluated)
Minimum laser blind hole diameter: Ø50 μm
BT / ABF / Substrate-like FR4

Send Gerber Files to Get a Quote

→View Mass Production Capacity Specifications

Reviewable upon signing an NDAFree DFM (Design for Manufacturability) AssessmentOne-on-One Layering Collaboration in Engineering

Cross-Section of a Typical Layered Structure

mSAP Semi-Additive Lamination · Laser Blind-Hole Interconnects

Mass Production Standards 20 / 20 μmPrototyping allows for evaluation 15 / 15 μmNumber of Floors Floors 2–16

BGA / CSP / FC / SiPComprehensive Coverage of All Major Packaging Types
BT / ABF / Substrate-like FR4A variety of material systems are available
C+2+2+C ~ 3+2+3Layered structures can be customized based on the layout
ENEPIG / ENIG / Hard GoldMainstream Surface Treatments for Substrates

Project Fit

First, determine what capabilities your IC carrier board project requires.

Engineers and procurement professionals typically do not start by looking for the “lowest price”; instead, they first verify whether the pin count, materials, package type, and mass production window are compatible. The four links below allow you to quickly locate the relevant information on this page.

High-Density / Fine-Line Projects

First, verify the trace width and spacing, laser blind vias, stack-up, copper thickness, and impedance, and then determine whether an mSAP or SAP routing is required.

View Manufacturing Capabilities →

BGA / CSP / FC / SiP

Verify the substrate, pads/bonding areas, surface treatment, and back-end packaging interfaces according to the packaging method.

View Packaging Options →

BT or ABF

The choice of materials should be determined by a combination of I/O density, line width and spacing, number of layers, signal requirements, package size, and cost targets.

View Material Selection →

Preparing for prototyping or moving to mass production

Submitting Gerber/ODB++ files, the layer stackup, materials, quantities, and critical tolerances together can reduce the number of back-and-forth confirmations.

View Quote Information →

Capability

IC Substrate Process Capability Parameters

The table below lists “Mass Production Base Capabilities” and “Prototyping Limit Capabilities.” The mass production base is used for preliminary manufacturability assessments; prototyping limits must be evaluated in conjunction with specific stack-ups, materials, copper thickness, and pattern density. Final capabilities, delivery times, and acceptance criteria are subject to engineering reviews and mutually agreed-upon documentation.

Parameter Items	Mass Production Capabilities	Maximum Proofing Capacity	Notes and Explanations
Minimum Line Width / Line Spacing	20 / 20 μm	15 / 15 μm	mSAP Semi-Additive Method + LDI (Laser Direct Imaging)
Minimum Laser Blind Hole Diameter	75 μm	50 μm	Supports plating to fill vias and via-on-via
Range of Floors	Floors 2–16	Floors 2–20	Layered structures such as C+2+2+C, 2+2+2, 3+2+3, etc.
Supporting Substrates	BT / ABF	BT / ABF / Substrate-like FR4	Materials can be selected based on the customer's specified brand and model
Thickness of the finished panel	0.15 to 2.0 mm	0.10 to 3.0 mm	For ultra-thin carrier substrates, warpage and strength must be evaluated simultaneously.
Maximum Panel Size	250 × 250 mm	250 × 250 mm	Supports delivery of single pieces, strips, or arrays
Impedance Control Tolerances	± 8%	± 7%	Single-ended / Differential; TDR impedance test report available upon request
Surface Treatment	ENEPIG / ENIG / Hard Gold / OSP	ENEPIG / ENIG	Chemically Deposited Nickel, Palladium, and Gold Are the Mainstream Choices for Substrates
Copper Thickness Range	9–35 μm	6–35 μm	Ultra-thin copper foil for etching fine circuits
Standard Delivery Time	Evaluation by Batch and Layering	5 to 10 business days	Limited to standard laminates and BT substrates, ≤ 8 layers; expedited processing is available through the fast-track process.

The data in the table is used for preliminary manufacturability screening; special structures, limit parameters, and mass production windows must all be confirmed through engineering reviews, and manufacturability should not be determined based on a single parameter alone.

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Key Parameters for Packaging and Reliability

The following are the items engineers most frequently verify during the carrier board selection process; you can refer directly to your packaging specifications.

Parameter Items	Capabilities / Specifications	Note
Warpage ＊	Review Based on Package Dimensions and Customer Specifications	Large-size FCBGA requires specialized simulation and tooling evaluation
Solder Ball Coplanarity ＊	Verify based on packaging specifications and measurement methods	Classified by package size; measured according to JEDEC methods
Minimum BGA Ball Pitch ＊	Specialized Review of Pad/Ball Structures	Subject to the combined constraints of solder ball size and stencil capacity
Minimum Inter-Key Spacing ＊	Specialized Review of Bonding Methods and Patterns	Suitable for wire-bond carrier boards
Sheet Thickness Tolerance	± 10% / Thin sheet ± 0.03 mm	For values below 0.2 mm, control based on absolute values
Dimensional Tolerances	± 0.10 mm Edge Milling / ± 0.05 mm Laser	Laser cutting is recommended for irregular shapes and high-precision contours
Solder Mask Alignment Accuracy	± 25 μm	The precision of window cutting directly affects the yield rate of ball planting.
ENEPIG Coating Thickness ＊	Confirmed in accordance with the customer's plating specifications	Can be adjusted according to customer specifications; a film thickness report is included with the shipment.
ENIG Coating Thickness ＊	Confirmed in accordance with the customer's plating specifications	Lower cost than ENEPIG; suitable for applications that do not require wire bonding
Key Parameters of the Substrate ＊	Verify based on the specified material grade / datasheet	The ABF system uses low loss values; high-frequency scenarios are subject to separate discussion.
Layered Structure	C+2+2+C / 2+2+2 / 3+2+3	Designed according to the number of layers, wiring density, and warpage requirements
Delivery Format	Single chip / strip / array	Determined based on the subsequent packaging process; vacuum anti-static packaging
Reliability Testing	TCT / HAST / HTS / PCT / Reflow Soldering Simulation	Internal reports can be provided; third-party reports will be arranged separately.

Items marked with an asterisk (*) are reference values based on typical substrate specifications; the engineering department will verify each item individually based on your packaging specifications before providing a formal quote.

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Differences in Circuit Precision Between IC Carrier Boards and Standard PCBs and HDI Boards

If your design falls within HDI's capabilities, you can have it verified by HDI first, as this offers better value in terms of both cost and lead time.

Sheets	Minimum Line Width / Spacing	Minimum pore size	Typical Number of Floors	Typical Applications
Standard PCB	75 / 75 μm	200 μm	Floors 2–8	General-Purpose Electronics, Industrial Control, Power Supplies
HDI Board	40 / 40 μm	100 μm	Floors 4–12	Mobile Phones, Consumer Electronics, Modules
IC Substrate	20 / 20 μm (mass production) \| 15 / 15 μm (prototyping)	50 μm	Floors 2–16	Chip Packaging, AI Computing Power, 5G Communications

Manufacturing & Evidence

Manufacturing Processes and Quality Verification

From fine-line routing and microvia filling to impedance testing, learn about the key verification steps in substrate manufacturing. The images below are provided for reference regarding processes and inspection methods; they do not represent actual photos of Jingpeng’s production lines, project test results, or certification documents. Actual capabilities and delivery materials are subject to project review and valid documentation.

Reference Diagram of Fine Circuit Cross-Sections — **Reference for Fine Circuit Cross-Sections**Observe the cross-section of the copper circuit and the morphology of the side walls; the image captions provide reference sample data.

Reference Image of a Copper-Filled Microporous Section — **Reference for Microporous Copper-Filled Slices**Observe the die geometry, copper filling morphology, and interface conditions through cross-sectional views.

Reference Diagram of LDI Exposure Equipment and Clean Production Environment — **LDI Laser Direct Imaging Equipment**Exposure Equipment and Cleanroom Environment Reference, used to illustrate the pattern transfer process.

Reference Diagram of an Ultraviolet Picosecond Laser Drilling System — **UV Laser Drilling Machine**Reference on ultraviolet picosecond laser drilling equipment, for understanding micro-hole processing methods.

Reference Chart for TDR Impedance Measurement Curves — **TDR Impedance Measurement Curve Reference**Identifying impedance changes through reflection curves; this is not the actual test report for this project.

Quality System Documentation ReviewISO 9001 logo illustration; the certificate holder, scope of certification, and validity period are subject to verification against valid documents.

Qualifications and System Certifications

ISO 9001 Quality Management System
UL Product Safety Certification
IPC-A-600 Visual Inspection / IPC-6012 Performance Specifications
RoHS and REACH Regulations on Hazardous Substances
Can be adapted to accommodate customer factory audits and system integration

Core Production Equipment

LDI Laser Direct Imaging Exposure System
× 2
UV Laser Drilling Machine
× 3
Fully Automated Electroplating and Via-Filling Line
× 1
Vacuum Molding and Laminating Systems
× 2
AOI (Automated Optical Inspection)
× 4
X-ray and Impedance Tester
× 2

Cleanroom Classification

Pattern Transfer and Exposure Area:
10,000-level
Compression and Laminating Area:
10,000-level
Other wet processes and post-processing steps:
100,000-class
Online Monitoring of Temperature, Humidity, and Particles Along the Entire Line

Engineering Team Support

One-on-One Collaboration with Substrate Process Engineers
Free DFM (Design for Manufacturability) Assessment Before Prototyping
Co-Design of Stacking and Impedance Schemes
Blueprints can be reviewed after signing an NDA
Ongoing process optimization during the mass production phase

Package Types

Supported Package Types and Application Areas

From consumer-grade modules to high-performance chip packaging, we offer customized substrate stacking designs and material solutions tailored to different packaging formats.

BGA

BGA Package Substrate

Ball grid array (BGA) packaging is currently the most widely used substrate form, utilizing bottom-side ball placement to achieve high-density interconnections between the chip and the motherboard. The core challenges with this type of substrate lie in the “escape routing” pressures caused by the large number of pins, as well as the design of thermal management paths to address increased chip power consumption. We typically use a BT substrate combined with a 4- to 16-layer laminate structure to achieve fan-out in the ball area with a production line width of 20/20 μm, and can improve thermal resistance through buried copper blocks and thermal via arrays.

Floors 4–16Mass Production 20/20 μmBT SubstrateBall pitch starting at 0.35 mm

Typical Applications:AI computing chips, FPGAs, memory chips, CPU/GPU modules, network processors

Get a Quote for BGA Substrates

CSP

CSP Package Substrate

Chip-scale packaging requires the substrate size to be close to that of the bare chip itself, with a focus on ultra-thin design, lightweight construction, and warpage control. Substrates as thin as 0.10 mm are highly prone to deformation during lamination and reflow, necessitating a comprehensive balance across all aspects—from core board selection and copper thickness distribution to lamination parameters. For our CSP projects, we employ ultra-thin core boards and a symmetrical laminate design, combined with laser cutting to ensure dimensional accuracy, and we conduct random coplanarity inspections prior to shipment to meet the miniaturization and assembly tolerances of end products.

Floors 2–8Sheet thickness starting at 0.10 mmUltra-thin Core BoardTotal surface area: Determined based on packaging specifications and measurement methods

Typical Applications:Wearable devices, smartphone camera modules, IoT sensors, memory, MEMS

Get a Quote for CSP Carrier Boards

FC Flip-Chip Packaging Substrate

In flip-chip packaging, the chip is mounted face-down and connected directly to the substrate via bumps; its interconnect density and electrical performance far exceed those of wire-bonding solutions, but it places the highest demands on the substrate’s warpage, surface flatness, and signal integrity. For such projects, ABF laminate materials are typically selected to achieve high-density routing and differential impedance design in 6- to 16-layer structures, with impedance tolerances controlled within ±8%. Warpage drift at reflow temperatures is suppressed through layer symmetry and press curve control.

Floors 6–16Impedance ± 8%ABF SubstrateWarp ≤ 0.10%

Typical Applications:5G/6G millimeter-wave, high-performance computing chips, network communication chips, high-speed SerDes interfaces

Get a Quote for FC Substrates

SiP

SiP (System-in-Package) Substrate

System-in-Package (SiP) technology integrates multiple heterogeneous chips and passive components onto a single substrate, resulting in a significant increase in routing density and the complexity of interlayer interconnects, while also requiring the management of signal crosstalk and power integrity issues between different chips. We support embedded component structures and multi-chip co-layout, engaging in stack-up and impedance planning from the design phase, helping customers balance routing paths, power planes, and thermal pathways within the limited area of the carrier board.

Floors 4–12Multi-chip LayoutEmbedded StructureDifferential Impedance Design

Typical Applications:Multi-chip integrated modules, RF front-end modules, medical electronics, in-vehicle domain controllers

Get a Quote for SiP Substrates

Material Selection

How to Choose Between BT and ABF Substrates

The substrate determines the cost range, achievable wiring density, and high-frequency performance of the carrier board, and is the first variable to be finalized during the selection process.

BT Substrate Bismaleimide Triazine

Cost-effective and offering good mechanical strength, this is the preferred choice for medium- and low-layer counts and standard line widths.

Typical Number of Floors: Mainly Floors 2 through 8
Economic Line Width: ≥ 20 / 20 μm
High-Frequency Performance: Generally, suitable for mid and low frequencies
Rigidity / Strength: High; consistent warpage performance
Cost Level: Relatively low

Suitable for:Memory chips, MEMS, consumer modules, CSPs, and low-to-medium-layer-count BGAs, as well as cost-sensitive and time-sensitive projects.

ABF Substrate Ajinomoto Build-up Film

With excellent dielectric properties, it allows for finer lines and a higher number of layers, making it the mainstream choice for high-end packaging.

Typical Number of Floors: Floors 6 through 16 and above
Economic Line Width: Up to 15 / 15 μm
High-Frequency Performance: Better; lower Df
Rigidity / Strength: It is relatively soft, so warping requires special control measures.
Cost Level: Relatively high

Suitable for:FC flip-chip packaging, high-performance chips, 5G/6G communications, high-speed SerDes, and other applications that demand high wiring density and signal integrity.

Four-Step Quick Assessment

If you check the following items in order, you should be able to determine the material type; if you're unsure, send us the specifications, and our engineering team will provide written recommendations.

1
View the number of floors
≤ 8 stories: BT is preferred; ≥ 10 stories or when high-density evacuation is required: switch to ABF
2
Check the line width
≥ 20/20 μm: BT is sufficient; ≤ 15/15 μm: ABF + mSAP is required
3
Check the frequency
Low-Loss ABF Systems for High-Speed Differential, Millimeter-Wave, and SerDes Applications
4
Consider the cost
Cost-sensitive and with ample performance headroom, BT offers better value for money.

Scope of Competence and Scope of Specialized Assessment

Ultra-high-end FCBGAs with line widths less than 15/15 μm and more than 20 layers must first undergo a process feasibility review.
To control warpage in large-size (single side > 80 mm) flip-chip substrates, it is necessary to perform a combined simulation of the package structure and the reflow profile.
Long-term mass-production orders specifying particular ABF grades that require securing original manufacturer production capacity must be scheduled in advance.
Wafer-level packaging (WLCSP / Fan-out) is part of the packaging and testing process and is not included in our factory’s substrate delivery scope; however, we can assist with referrals.
If your design features line widths of 40/40 μm or greater and has 12 layers or fewer, HDI boards can typically significantly reduce costs and lead times; we would therefore recommend that you first conduct an HDI validation.

Process & Quality

Manufacturing Processes and Quality Control

From design review to shipment of finished products, the entire process is carried out on dedicated carrier board production lines and in cleanrooms, with key processes subject to digital monitoring and control under the 100% system.

01
Design Review and DFM
Analyze Gerber / ODB++ files, generate manufacturability analysis reports, and verify the layer stackup, impedance, and trace width schemes.
02
Material Selection and Incoming Inspection
Select the BT/ABF substrate and copper foil specifications based on the application scenario, and specify the incoming material batches and key parameters.
03
Graphics and Exposure
LDI (Laser Direct Imaging), combined with the mSAP (semi-additive process), enables the fabrication of fine lines at the 20-micrometer level.
04
Laser Drilling
UV laser via formation, with blind vias as small as 50 μm; supports via-filling and stacked via interconnect structures.
05
Electroplating and Via Filling
Full-board plating + selective plating, controlling the uniformity of the copper thickness to ensure that the holes are fully filled without voids.
06
Vacuum Laminating and Alignment
Vacuum lamination, precision control of interlayer alignment, and suppression of substrate warping.
07
Surface Treatment
ENEPIG, ENIG, hard gold, and other surface treatments; film thickness is controlled in accordance with specifications to ensure solderability.
08
Inspection and Shipping
AOI + flying probe testing and specialized fixture electrical testing + X-ray inspection; shipped with an inspection report.

Tiered Clean Production

The pattern transfer and lamination processes are performed in a Class 10,000 cleanroom, while the remaining processes are conducted in a Class 100,000 cleanroom to control particulate matter and defect rates.

AOI + Electrical Testing: Dual Coverage

Automatic optical inspection is combined with flying probe testing and electrical testing using specialized fixtures to cover critical items such as open circuits, short circuits, and circuit defects.

X-ray and Microscopic Analysis

Verify the quality of blind vias and filled vias using X-ray and metallographic section analysis to ensure interconnect reliability.

Reliability and Shipment Data

We offer reliability testing services such as TCT, HAST, and HTS, and provide impedance and film thickness test data with each shipment.

From Prototype to Mass Production

The Three Stages from Prototyping to Mass Production

MOQs, lead times, and pricing structures vary depending on the stage of the process, so be sure to understand these details before deciding where to start.

Phase One

Prototype Validation

Minimum Order Quantity: 5 to 20 pieces
Standard Delivery Time: 5 to 10 business days
Capability Criteria: Advanced Capabilities—Subject to Review
Quotation Methods: Based on engineering costs + manufacturing costs
Sample Policy: Prototype fees can be applied toward mass production costs

Phase Two

Small-batch trial production

Minimum Order Quantity: 50 to 500 pieces
Standard Delivery Time: By Layer Evaluation
Capability Criteria: Nearing mass production
Quotation Methods: Tiered Unit Price
Sample Policy: Synchronize the Output of Yield Reports

Phase Three

Mass Production

Minimum Order Quantity: Production Scheduling by Batch
Standard Delivery Time: By Batch and Production Schedule
Capability Criteria: Mass Production Capabilities
Quotation Methods: Volume Pricing + Annual Negotiated Pricing
Sample Policy: Ongoing Process Optimization and Follow-up

For specific rules regarding the deduction of prototyping fees from mass production costs, as well as the eligibility criteria and rates for the expedited "green channel," please confirm these details with the engineering team when requesting a quote.

FAQ

Frequently Asked Questions About Custom IC Substrates

Below are the questions customers most frequently ask regarding IC carrier board prototyping and mass production. If you need further clarification, please contact our engineering team directly.

What is the difference between the line width on your mass production line and the line width on your prototyping line?

The mass production benchmark capability is 20/20 μm...this is a standard that can be included in the contract and consistently applied across bulk orders; The maximum resolution for prototyping is 15/15 μm...Feasibility can only be determined after the specific stacking, pattern distribution, and materials have been confirmed.

The purpose of distinguishing between the two is to avoid discrepancies between expectations and reality during mass production. If your design requires 15/15 μm and is intended for mass production, we recommend conducting a mass production feasibility assessment concurrently with the prototyping phase; we will clearly inform you whether the design can be scaled up to mass production.

What is the difference between a BT substrate and an ABF substrate? How should I choose between them?

BT (bis-maleimide triazine) substrateWith relatively low cost and good mechanical strength, it is suitable for BGA and CSP packaging applications with a small number of layers and line width requirements of 20 μm or greater, and is widely used in memory chips, MEMS, and consumer modules.

ABF (Ajinomoto Build-up Film) SubstrateWith superior dielectric properties, it enables finer lines and higher layer counts, making it suitable for flip-chip (FC) packaging, high-performance chips, 5G communications, and other applications with stringent requirements for signal integrity and routing density; however, it involves higher costs and greater manufacturing complexity.

Selection Tips:Consider the number of layers, trace width requirements, and signal frequency. For boards with ≥ 10 layers, line widths ≤ 15 μm, or high-frequency, high-speed applications, ABF is the preferred choice; for projects with low to medium layer counts or where cost is a key consideration, BT offers better value for money.

Will the drawings and documents be kept confidential? Can we sign an NDA?

Sure.We are willing to sign a confidentiality agreement before receiving the drawings, and we are also open to using your company’s version of the NDA template. If you do not yet have a template, please contact our business representative to request our standard version.

In terms of internal procedures, client drawings are used solely for engineering evaluations and quotations, and access is restricted to personnel necessary for the project; file uploads and storage are managed on a project-by-project basis, and relevant files may be deleted upon request after a project is completed or terminated.

How long does it take to produce a prototype IC carrier board? What is the minimum order quantity for small batches?

The lead time for prototyping standard IC carrier boards is 5 to 10 business days, Applicable conditions: standard stacking, BT substrate, ≤ 8 layers; Stacking with a higher number of layers or ABF materials requires a separate evaluation. Rush orders may be eligible for expedited processing; delivery times will be confirmed separately.

The proofing stage typically 5 to 20 piecesProduction can begin immediately; for small-batch trial production, we recommend 50 to 500 pieces; for mass production orders, pricing is based on the stack-up and production schedule. Prototyping costs can be offset against subsequent mass production orders according to established rules; please confirm the specific rules when requesting a quote.

What types of carrier boards do you offer for customization?

Currently supported BGA, CSP, FC (Flip Chip), SiP (System-in-Package) Custom substrate manufacturing for the four major packaging types, as well as for derivative packaging formats such as COB and QFN.

The number of layers ranges from 2 to 20 (with a mass production commitment for 2 to 16 layers). We support BT, ABF, and substrate-like FR4 base materials, and can select materials based on the brand and model specified by the customer. If your package type falls outside the above range, please send us your package drawings for a specialized evaluation.

What information is required for an IC carrier board quote?

To provide an accurate quote, please provide the following information:

1. Gerber or ODB++ files(Required)
2. Layered Structure and Number of Layers Requirements
3. Substrate and Surface Treatment Requirements(BT / ABF, ENEPIG / ENIG, etc.)
4. Quantity(Prototype Quantity and Estimated Mass Production Volume)
5. Delivery Requirements

If you don't have the complete drawings yet, you can still provideSpecification Requirements (Number of Layers, Line Width, Dimensions, Quantity), We can provide a reference price range for now and issue a formal quote once the drawings are complete.

How accurate is the impedance control of the IC carrier board? Can you provide a test report?

The impedance control tolerance for mass production is ± 8%, Prototypes can be produced ± 7%, supports single-ended and differential impedance designs, and shipments can be accompanied by TDR impedance test reports, as well as cross-sectional and film thickness data.

For high-frequency, high-speed applications (such as 5G/6G communications and high-speed SerDes interfaces), we recommend consulting with our engineering team regarding the layer-up scheme during the design phase so that material selection and line width design can be optimized in advance.

How is warpage controlled? What reliability tests are available?

We control warpage through symmetrical stack-up design, optimization of the press curve, and balanced copper thickness distribution. Warpage targets must be determined based on package dimensions, stack-up, copper distribution, and customer specifications; for large-size flip-chip substrates, target values must be determined after performing joint simulations that consider both the package structure and the reflow profile.

In terms of reliability, we can provide TCT (Temperature Cycling), HAST (Highly Accelerated Temperature and Humidity Testing), HTS (High-Temperature Storage), PCT (Pressure Cooker Testing) In addition to reflow soldering simulation testing, we can provide internal reports; third-party reports require a separate scheduling process.

Can we conduct an on-site audit at your facility? Can you assist with integration into our customer’s system?

Sure.We work with our clients to conduct supplier audits and on-site factory inspections, and can provide system documentation, process flow charts, and a list of testing capabilities in advance. Following the audit, we provide feedback on corrective actions and follow up to ensure they are fully resolved. For projects that have entered mass production, we can provide periodic quality data as needed.

What are the delivery options? What are the packaging and shipping standards?

You can press Single, strip, array (multi-panel) There are three delivery formats; the specific method will be determined based on the loading process for the subsequent packaging stage.

Products are shipped in vacuum-sealed, anti-static packaging, accompanied by a desiccant and a humidity indicator card. The outer carton is labeled with the lot number and traceability code to facilitate incoming inspection and issue tracing.

RFQ Checklist

Before requesting a quote for IC carrier boards, we recommend that you prepare the following information

The more complete the documentation, the easier it is for the engineering team to assess manufacturability, risk factors, delivery times, and costs accurately the first time. Even without complete drawings, a preliminary assessment at the parameter level can still be conducted.

It is recommended that this be submitted along with the RFQ.

Gerber / ODB++ / IPC-2581 Manufacturing Data
Number of Layers, Layered Structure, and Final Thickness
BT / ABF or specified material grade
Minimum Line Width/Spacing, Minimum Hole Diameter, and Via Structures
Impedance, Copper Thickness, Surface Treatment, and Key Tolerances
Single Chip / Strip / Array Delivery Formats and Dimensions
Prototype Quantity, Estimated Mass Production Quantity, and Target Delivery Date
Special Reliability Requirements, Test Reports, or Customer Specifications

What Should Be Included in an Engineering Review?

Manufacturability Findings and DFM Items Requiring Revision
Are the limit parameters applicable only to the sample, or do they fall within the mass production window?
Recommended Materials, Laminate Structures, and Surface Treatment Solutions
Key Risks: Warpage, Alignment, Copper in Holes, Impedance, Plating, etc.
Quotation and Delivery Time Standards for Samples, Small Batches, and Mass Production
Acceptance Criteria Requiring Additional Confirmation from the Customer

Sensitive Items:You may sign an NDA first and then submit the complete design documentation. The performance specifications listed on this page are for preliminary screening purposes; the final specifications will be determined based on the project’s DFM and mutual agreement between both parties.

Send your Gerber files to get a customized quote for your IC carrier board

Fill out the form on the right or send your information directly to one of our engineers. Once we receive your information, we will first conduct a manufacturability assessment, and then provide you with a detailed quote and delivery schedule—the assessment itself is free of charge.

Contact the engineering team directly

Drawings: Gerber / ODB++ / IPC-2581
Engineering Documentation: Lamination, Materials, Impedance, and Key Tolerances
NDA: Sensitive projects may be signed prior to review

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Online Quote Request

Fields marked with * are required. You may submit your parameter requirements even if you do not have drawings.

Number of Floors

Minimum Line Width / Line Spacing

Substrate

Surface Treatment

Quantity

Expected Delivery Date

Design Files (Gerber / ODB++ / Layer List)

Select a file or drag and drop it here

Supports ZIP, RAR, and ODB++ archives; individual files should preferably not exceed 50 MB.

Contact

Phone Number

Corporate Email

Additional Information

Confidentiality of Information:Submitted drawings are intended solely for engineering evaluation and quoting purposes and will not be disclosed to third parties; If you need to sign a non-disclosure agreement (NDA) first, please check the box below or indicate this in the remarks section. We will prioritize issuing the NDA before accepting your files.

I would like to sign an NDA before providing the drawings. Please contact me first.