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<\/p>\nMost PCBs in today\u2019s electronic products contain high-speed signal networks to some extent. When designing circuits and PCBs, it is essential to pay close attention to the signal integrity of these networks. For many engineers, \u201csignal integrity\u201d sounds like a simple concept, but it often proves to be a major headache for hardware or PCB design engineers. This article focuses primarily on PCB design to examine which factors can lead to signal integrity issues during the design process.<\/p>\n
<\/p>\n
The choice of PCB material directly affects signal integrity. For example, parameters such as the dielectric constant, loss tangent, copper foil roughness, and glass fiber cloth of the PCB material all influence the electrical performance of the signal. The following graphs show how the dielectric constant and loss tangent of PCB materials vary with frequency.<\/p>\n
PCB material is the foundation, so it is important to select the appropriate PCB material before designing a PCB.<\/p>\n
Layer stacking is a critical step in PCB design. If the layer stacking is improper, it can directly lead to inherent signal integrity issues in the design.<\/p>\n
For example, when designing laminates, we typically select materials based on thickness; however, even for the same material, there are many different types of PP or core materials, and their performance characteristics\u2014such as the electrical parameters Dk\/Df and glass fiber specifications\u2014are not identical.<\/p>\n
Although they are the same thickness, one consists of a single 2116 PP layer, while the other consists of two 1080 PP layers. Their Dk and Df values are not the same. Therefore, if these materials are used indiscriminately when designing a laminate structure, it could lead to signal integrity issues. Additionally, the glass fiber used in the 1080 and 2116 materials is different.<\/p>\n
For high-speed signals, it is also important to consider the effects of the glass fiber effect. We have previously discussed the glass fiber effect in earlier sections.<\/p>\n
The trace width of a transmission line is determined by its impedance. First, determine the impedance of the transmission line based on the requirements of the bus or chip platform; then, use that impedance to calculate the trace width in ADS CILD.<\/p>\n
When designing PCBs, engineers aim for consistent trace widths to maximize design efficiency. However, this is difficult to guarantee because many components\u2014such as chips and connectors\u2014may have small pitches or high pin densities, which can force the trace width to be reduced during the design process. Changes in trace width can compromise signal integrity. During the design process, efforts should be made to minimize these line width variations or to shorten the length of the affected sections, among other strategies. If there are too many transmission lines, you can also consider using the RapidScan-Z feature in ADS SIPro to identify line width variations\u2014that is, points of impedance discontinuity.<\/p>\n
In PCB design, there are many types of spacing for transmission lines, such as the spacing within a differential pair and the spacing between different types of transmission lines. Different types of spacing have different requirements. For example, the spacing between differential pairs should not be too close (small) nor too far apart (large), as determined by impedance and design requirements. When it comes to spacing between different types of transmission lines, it is desirable to keep the spacing as wide as possible to minimize crosstalk between them; however, due to space and cost constraints, this spacing cannot be reduced indefinitely. The following shows the trend in crosstalk as the spacing changes.<\/p>\n
The length of a transmission line is determined by the product\u2019s structure and actual design. Unless there are specific requirements, it is generally preferable to design the transmission line to be as short as possible. This is because the longer the transmission line, the greater the signal attenuation and the greater the energy loss. If the transmission line is indeed very long and cannot be shortened, you may consider using low-loss board material or installing a repeater along the link.<\/p>\n
The concept of \u201cequal length\u201d was actually devised by engineers as a \u201cclever shortcut.\u201d So let\u2019s continue to use this concept in our discussion. Transmission line equal length includes equal length within a differential pair as well as within a group of transmission lines of the same type. If transmission lines are not of equal length, it can lead to signal integrity issues, including timing violations, excessive loss, or susceptibility to interference. The simplest way to address this is to route the differential pair so that the two segments of transmission line are of equal length. However, as mentioned in previous articles, this method of achieving equal length through routing does not fully meet design requirements from an electrical perspective. It is best to make appropriate adjustments to ensure that the propagation delays of the transmission lines are consistent. Particular attention must be paid to equal-length design, especially for groups of transmission lines (such as DDR buses).<\/p>\n
A High-Speed Circuit Design Issue That Even 90% Engineers Didn't Realize: The Impact of Equivalent-Length Windings<\/p>\n
In PCB design, engineers often inadvertently create transmission lines that span partition lines. While this may not be a problem for low-speed signals, it can lead to catastrophic results for high-speed signals. Spanning partition lines can cause issues such as impedance discontinuities, reflections, timing problems, and signal radiation. Clearly, designs that span partition lines result in slightly inferior performance. In PCB design, if a split-crossing design is unavoidable, the length of the split-crossing transmission lines should be minimized as much as possible. This is especially true when signal rates are high (such as 25 Gbps); in such cases, any occurrence of a split-crossing must be carefully evaluated, and every effort should be made to avoid it.<\/p>\n
With the advancement of electronic technology, an increasing number of buses are adopting point-to-point designs; however, some buses still retain a multi-topology design, such as the DDR bus, which consists of clock, address, control, and command signal lines.<\/p>\n
The design of a flyby topology can potentially cause impedance discontinuities. To resolve signal integrity issues caused by such structures, it is necessary to properly compensate for transmission line impedance, terminate the lines (or adjust the ODT), and so on.<\/p>\n
Vias are indispensable in the design of multilayer PCBs. For transmission lines, vias often cause signal integrity issues such as impedance discontinuities and increased loss. When designing vias for transmission lines carrying high-speed or high-frequency signals, it is necessary to optimize the via structure\u2014including drill hole size, pads, anti-pads, via stubs, and so on.<\/p>\n
The design of the power supply system is the most critical aspect of electronic product design, and it is also the area most prone to problems. In increasingly complex electronic systems, a single system may contain more than 10 power supply units\u2014or even more.<\/p>\n
For engineers working on system products, designing a good power supply primarily involves two aspects: the circuit design of the power supply system and the PCB design of the power supply system. When designing the PCB, it is essential to consider the layout and design of the power planes, as well as the placement of filtering capacitors. To ensure these power supplies are designed as effectively as possible, it is advisable to perform power integrity simulations both at the beginning of the design process and upon its completion, in order to identify potential issues as early as possible.<\/p>\n
As electronic product designs become increasingly complex, faster, and more compact, PCB design has grown more challenging, and signal integrity issues have become more prevalent\u2014and these problems are by no means limited to those discussed in this article. Regardless of the type of design, it is essential to maintain good design practices throughout the process and to make full use of simulation tools for analysis both before and after design.<\/p>","protected":false},"excerpt":{"rendered":"
Most PCBs in today\u2019s electronic products contain high-speed signal networks to some extent. When designing circuits and PCBs, it is essential to pay close attention to the signal integrity of these networks. For many engineers, \u201csignal integrity\u201d sounds like a simple concept, but it often proves to be a major headache for hardware or PCB design engineers. This article focuses primarily on PCB design to examine which factors can lead to signal integrity issues during the design process.<\/p>","protected":false},"author":1,"featured_media":805,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"slim_seo":{"title":"10 Signal Integrity Issues in High-Speed PCB Design","description":"What are the 10 signal integrity issues in high-speed PCB design? This article explains the causes and mitigation strategies for each issue\u2014from board material and stack-up, trace width and spacing, equal-length matching, and cross-cut design to vias and power systems\u2014one by one."},"_slim_seo_primary_term_category":0,"_slim_seo_primary_term_post_tag":0,"footnotes":""},"categories":[26],"tags":[32],"class_list":["post-541","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","tag-pcb"],"_links":{"self":[{"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/posts\/541","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/comments?post=541"}],"version-history":[{"count":1,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/posts\/541\/revisions"}],"predecessor-version":[{"id":19116,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/posts\/541\/revisions\/19116"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/media\/805"}],"wp:attachment":[{"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/media?parent=541"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/categories?post=541"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jingpengpcb.com\/en\/wp-json\/wp\/v2\/tags?post=541"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}